The present invention relates generally to data communication systems and more particularly relates to an adaptive data slicer circuit based on peak detectors having dynamic selection of operating parameters.
Data slicers, well known in the electrical arts, are commonly used in communications receivers to recover the digital data at the output of a demodulator. For example, in a frequency shift keying (FSK) receiver, such as that used in a communications system constructed in accordance with the Bluetooth specification, a common realization of the demodulator is as a frequency discriminator operating at some intermediate frequency (IF). The discriminator functions to recover the original baseband signal from the IF signal.
In the typical system, the signal at the output of the demodulator can be represented as a combination of (1) the original baseband signal used to convey the data transmitted by the transmitter; (2) additive noise and interference contributed by the wireless channel; and (3) the distortion caused by the actual circuitry the signal passes through. At the output of the demodulator, a decision circuit known as a xe2x80x98data slicerxe2x80x99 is typically used to convert the baseband signal into a stream of data bits. It is the goal of the data slicer to perform this conversion such that the content of the data bits match closely as possible the content of the original transmitted data.
In addition to reproducing the transmitted data with a minimum bit error rate (BER), the data slicer should be able to overcome variations in the properties or characteristics of the signal. Such variations may be due to receiving signals from multiple transmitters and may include variations in modulation factors and carrier frequency errors such as drift. Thus, it is desirable to have a data slicer whose slicing threshold (which is used to compare the baseband signal with) is determined adaptively and is not fixed at a predetermined level. The optimum slicing threshold level should be determined independently for each received packet and should be adapted throughout reception of the packet to compensate for possible frequency droop during its transmission.
As described above, the frequency offset and other parameters of the received signal in a communications system could have an effect on the DC level of the recovered baseband signal at the output of the demodulator (e.g., at the output of a FM discriminator). Consequently, the optimal slicing threshold is not fixed and typically varies over time. Depending on the application, it is preferable and sometimes necessary, for the slicing circuit to be sufficiently dynamic and adaptive to determine the optimum threshold for data slicing for each packet received, usually at the beginning of the packet during the preamble.
With the advent today, however, of wireless communications systems employing packets having a shortened length and shortened time slots, this becomes difficult to achieve with prior art slicing circuits. For example, the packets used in the Bluetooth protocol comprise a short 4-bit preamble and are transmitted using a spread spectrum frequency hopping scheme wherein the slot times are 625 xcexcsec. The high hopping rate, short slot times and short preamble dictate that the data slicer be able to very quickly adapt the slicing decision threshold used to generate the received digital data.
On the other hand, in order to minimize the BER in the recovery of the payload contents of the packet, the slicing threshold should remain close to optimal with minimal variations thereto. This, however, creates conflicting requirements for the time constants associated with the determination of the slicing threshold. On the one hand, it is desirable to have quick adaptation of the slicing threshold during packet acquisition (i.e., during the preamble, etc.) and on the other hand it is desirable to have slow adaptation of the slicing threshold during reception of the payload in order to minimize the BER.
For example, in the Bluetooth protocol, the payload is preceded by an access code that is able to tolerate a higher BER. It is desirable, therefore, to determine the optimal slicing threshold level during reception of the access code even though the BER may be relatively high. After a valid access code is detected, it is desirable if the slicer could utilize longer time constants thus yielding a more stable slicing level during the reception of the payload portion of the packet.
Several examples of prior art adaptive slicing circuits will now be presented. A block diagram illustrating a first prior art data slicer circuit that utilizes a RC combination for smoothing the input voltage is shown in FIG. 1. The data slicer, generally referenced 10, comprises a slicing comparator 16 and a RC combination made up of resistor 12 having a value R and capacitor 14 having a value C. In operation, the RC functions to smooth the input voltage VIN such that an average of the voltage over time is input to the inverting terminal of the op amp. The principle is that over time, the capacitor functions to smooth the input voltage. Over time, the voltage across the capacitor represents the average of the input voltage and is used as the threshold or slicing voltage for determining the output data. The slicing comparator functions to compare the input voltage to the average voltage developed across the capacitor. If the input voltage is greater, a xe2x80x981xe2x80x99 is output and if the input voltage is lower, a xe2x80x980xe2x80x99 is output.
A disadvantage of this data slicer circuit is that is cannot quickly adapt to packets having a relatively short length. Optimum performance is achieved only when the circuit is configured to adapt slowly and using long packets having substantially equal numbers of 0""s and 1""s. The performance of the circuit severely degrades with short packets that may contain long sequences of 0""s or 1""s. In such a circuit, the use of a fast time constant for C results in degraded performance in terms of BER and may result in the loss of synchronization.
A block diagram illustrating a second prior art data slicer circuit that utilizes a DC blocking capacitor is shown in FIG. 2. The data slicer, generally referenced comprises a slicing comparator 26 (hard limiter or 1 bit A/D), capacitor 22 having a value C and a resistor 24 having a value R. In operation, the capacitor cancels the DC level since the voltage across the capacitor is subtracted from the input voltage. The input voltage across the resistor now swings through zero. To generate the output data, the voltage across R is compared with the slicing voltage that can comprise a voltage fixed at ground level. Since the capacitor functions to cancel the DC, any fluctuations represent peaks of the signal. The slicing comparator outputs a xe2x80x981xe2x80x99 for voltage swings above ground and a xe2x80x980xe2x80x99 for swings lower than ground.
The disadvantages of this circuit are similar to those of the first prior art slicer described above. The circuit cannot quickly adapt to packets having a relatively short length. High performance is achieved only with slow adaptation, i.e., long time constant for C, and when using long packets having substantially equal numbers of 0""s and 1""s. The performance of the circuit severely degrades with short packets that may contain long sequences of 0""s or 1""s. In such a circuit, the use of a fast time constant for C results in degraded performance in terms of BER and may result in the loss of synchronization.
A block diagram illustrating a third prior art data slicer circuit that utilizes two diodes in parallel is shown in FIG. 3. The data slicer, generally referenced 30, comprises a slicing comparator 38, diodes 32, 34 and capacitor 36 having a value C. In operation, the capacitor is charged and discharged through the diodes so that its voltage tracks the average of the peaks of the input signal. For optimal operation of the circuit, the peak to peak voltage of the input signal is preferably two times the diode drop (i.e., 1.2 VP-P for 0.6 V silicon diodes). Thus, the amplitude of the input signal is adjusted so as to have a direct relationship with the forward biasing voltages of the diodes.
A disadvantage of this circuit is that the performance of the circuit (measured in BER versus Eb/No or SNR) is degraded with variations in the peak to peak voltage of the input signal.
Consider the case where the input signal comprises the output of an FM discriminator. In this case, the variations in the peak to peak of the output voltage may be caused by variations in the modulation index, variations in the gain of the discriminator and by additive noise introduced by the channel and/or the receiver circuitry itself.
Even in the case where such variations do not occur and in the absence of additive noise, however, a degradation of performance can occur due to the data itself being transmitted. In other words, the peaks recovered in the baseband circuitry (i.e., by the discriminator) vary in accordance with the data transmitted due to the ISI inherent in the signal. In all three prior art data slicing schemes presented above, optimum circuit operation is achieved only when the data being transmitted consists of a substantially equal number of 0""s and 1""s. In addition, optimum performance is only achieved after long periods of time and when the circuits are configured with a relatively long time constant. A long time constant is achieved by using a relatively large capacitance in all three circuits 10, 20, 30. Thus, the prior art circuits perform well only in cases where the packets or messages being sent are relatively long and the contents comprise nearly equal numbers of 0""s and 1""s.
In cases where the packets sent are relatively short and the number of 0""s and 1""s are not necessarily equal, the prior art circuit""s BER performance is severely degraded. The circuit of FIG. 3, however, has reasonable performance degradation even when these conditions are not satisfied. For example, the relatively short preamble and short packet lengths of the transmission signals specified by the Bluetooth protocol do not permit the use of large time constants in the data slicer. The use of large time constants would help smooth out the slicing voltage input to the slicing comparator. Their use, however, with short packets such as used in the Bluetooth protocol is precluded due to the degradation of performance.
An adaptive data slicer may also be realized digitally using digital sampling and processing. When integrated together with the transceiver on a single integrated circuit, however, such a data slicer would likely consume relatively large amounts of current, take up large areas of silicon and may possibly be a source of noise when high data rates, e.g., 1 Mbps of Bluetooth, are used.
The present invention is an adaptive data slicer which functions to adapt to a changing input signal by producing the optimal slicing threshold for use in a decision circuit. The data slicer utilizes two peak detectors: (1) a maximum peak detector for detecting the highest levels of the input signal typically corresponding to sequences of 1""s in the transmitted data and (2) a minimum peak detector for detecting the lowest levels of the input signal typically corresponding to sequences of 0""s in the transmitted data. The peak detector outputs are averaged to obtain the optimal slicing threshold. This threshold is then used to determine the received digital data.
The data slicer incorporates adaptation circuitry that is operative to dynamically adjust the discharge rate of the holding circuits in the two peak detectors. A discharge processor functions to generate a control signal used to control the discharge rate, i.e., time constants or discharging current, of both peak detectors. The maximum peak detector is discharged to ground while the minimum peak detector is discharged to the supply voltage.
The control signal is generated in accordance with a particular function chosen to exhibit desired discharge properties. The input to the function is the difference between the two peak detector output signals. Thus, the data slicer is able to quickly adapt to varying signal parameters or conditions while maintaining enhanced performance. The function may be chosen to provide any desired discharge characteristics. Note that both linear and non-linear functions may be used with the invention.
A simplified example of a discharge processor is presented wherein the discharge rate is accelerated by a predefined amount when the two peaks detector output signals deviate more than a certain threshold. In addition, discharge is disabled when the two peaks detector output signals deviate below a certain threshold.
The benefits of the adaptive data slicer presented herein include (1) enabling its analog implementation within an integrated RF transceiver without the use of digital processing and the drawbacks associated therewith, (2) the required silicon area and current consumption in realizing the adaptive data slicer is quite reasonable, (3) high performance (i.e., low BER) for a received signal exhibiting variations in signal properties, and (4) substantially no packet loss due to the failure of the data slicer to adapt to changes in the input signal.
The adaptive data slicer is applicable to numerous types of communications systems. In particular, the present invention is applicable for use in communication systems employing FSK modulation. In particular, the invention is applicable for use in an FSK receiver constructed in accordance with the Bluetooth specification or DECT compatible communication systems. The signal input to the adaptive data slicer would, in this case, comprise the output of the FM discriminator portion of the receiver or the output of any other type of demodulator.
There is thus provided in accordance with the present invention an adaptive data slicer for generating digital data from an input signal comprising a maximum peak detector for detecting the highest levels of the input signal and for generating a maximum peak detection signal therefrom, a minimum peak detector for detecting the lowest levels of the input signal and for generating a minimum peak detection signal therefrom, a first discharge circuit adapted to discharge the maximum peak detector signal to ground in accordance with one or more discharge control signals, a second discharge circuit adapted to discharge the minimum peak detector signal to a supply voltage in accordance with the one or more discharge control signals, a processor adapted to generate the one or more discharge control signals in accordance with a function of the maximum peak detection signal and the minimum peak detection signal, averaging means for generating an averaged signal representing the average of the maximum peak detection signal and the minimum peak detection signal and decision means for comparing the input signal with the averaged signal so as to generate a xe2x80x981xe2x80x99 when the input signal is greater than the averaged signal and to generate a xe2x80x980xe2x80x99 when the input signal is less than the averaged signal.
There is also provided in accordance with the present invention a method for adaptively data slicing an input signal and generating digital data therefrom, the method comprising the steps of detecting the highest levels of the input signal and generating a maximum peak detection signal therefrom, detecting the lowest levels of the input signal and generating a minimum peak detection signal therefrom, discharging the maximum peak detector signal to ground in accordance with a first function whose input includes the maximum peak detection signal and the minimum peak detection signal, discharging the minimum peak detector signal to a supply voltage in accordance with a second function whose input includes the maximum peak detection signal and the minimum peak detection signal, generating an average signal representing the average of the maximum peak detection signal and the minimum peak detection signal and comparing the input signal with the averaged signal so as to generate a xe2x80x981xe2x80x99 when the input signal is greater than the averaged signal and to generate a xe2x80x980xe2x80x99 when the input signal is less than the averaged signal.
There is further provided in accordance with the present invention a Frequency Modulation (FM) communications receiver comprising a receiver front end for converting a signal received from a channel to an Intermediate Frequency (IF) signal, an IF filter coupled to the receiver front end and adapted to filter the IF signal, an FM demodulator adapted to convert the output of the IF filter to a baseband signal, a baseband filter coupled to the FM demodulator and adapted to filter the baseband signal and an adaptive data slicer comprising means for detecting the highest and lowest levels of the baseband signal and generating a maximum peak signal and minimum peak signal, respectively, averaging means for generating an averaged signal representing the average of the maximum peak detection signal and the minimum peak detection signal, decision means for comparing the baseband signal with the averaged signal so as to generate a xe2x80x981xe2x80x99 when the baseband signal is greater than the averaged signal and to generate a xe2x80x980xe2x80x99 when the baseband signal is less than the averaged signal and means for discharging the maximum peak signal to ground and the minimum peak signal to a supply voltage in accordance with a function of the maximum peak signal and the minimum peak signal.